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CXK77920TM/YM-11/12/15
262144-word x 9-bit High Speed Synchronous Static RAM
Description The CXK77920TM/YM is a high speed CMOS synchronous static RAM with common l/O pins, organized as 262144-word-by-9-bit. This synchronous SRAM integrates input registers, high speed SRAM and output registers onto a single monolithic IC. All input signals are latched at the positive edge of an external clock (CLK). The RAM data from the previous cycle is presented at the positive edge of the subsequent clock cycle. Write operation is initiated by the positive edge of CLK and is internally self-timed. This feature eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals. 90MHz operation is obtained from a single 5V power supply. Function There are three possible user transactions with the STRAM: Read operation, write operation and deselect operation. * The read operation requires WE = "HIGH" and OE = CE = "LOW" on the positive edge of CLK. The memory location pointed to by the contents of the Address registers is read internally and the contents of the location are captured in the Data-out registers on the next positive edge of CLK. The state of Data-out will reflect the contents of the Data-out registers. * The write operation requires CE = WE = "LOW" on the positive edge of CLK. The memory location pointed to by the contents of the Address registers is written with the contents of the Data-in registers. The write operation is entirely self-timed, eliminating critical timing edges. * The deselect cycle requires CE = "HIGH" or OE = WE = "HIGH" on the positive edge of CLK. Write operation and internal read operation are disabled during the clock cycle. The data outputs are forced to a high impedance state during the next clock cycle. During the deselect cycle by CE = "HIGH", STRAM turns to power down mode. CXK77920TM 44pin TSOP (II) (Plastic) CXK77920YM 44pin TSOP (II) (Plastic)
Structure Silicon gate CMOS IC Features * Fast cycle time: CXK77920TM/YM-11 CXK77920TM/YM-12 CXK77920TM/YM-15 * Fast clock to data valid CXK77920TM/YM-11 CXK77920TM/YM-12 CXK77920TM/YM-15 6.0ns 6.5ns 7.0ns (Cycle) 11.0ns 12.5ns 15.0ns (Frequency) 90MHz 80MHz 66.7MHz
* High speed, low power consumption * Single +5V power supply: 5V5% * Separate output power supply: 3.15 to 5.25V * Inputs and outputs are TTL compatible (3.3V l/O compatible) * Common data input and output * All inputs and outputs are registered on a single clock edge * Self-timed write cycle * Package line-up: 400mil, 44 pin TSOP II with 0.8mm pitch
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E93Z08-ST
CXK77920TM/YM
Pin Configuration (Top View)
CXK77920TM A17 A16 A15 A14 A13 CE VSSQ I/O8 I/O7 VCCQ VCC VSS VSSQ I/O6 I/O5 VCCQ WE A12 A11 A10 A9 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 A3 OE VCCQ I/O0 I/O1 I/O2 VSSQ VSS VCC VCCQ I/O3 I/O4 VSSQ CLK A4 A5 A6 A7 A8 A0 A1 A2 A3 OE VCCQ I/O0 I/O1 I/O2 VSSQ VSS VCC VCCQ I/O3 I/O4 VSSQ CLK A4 A5 A6 A7 A8
CXK77920YM 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A17 A16 A15 A14 A13 CE VSSQ I/O8 I/O7 VCCQ VCC VSS VSSQ I/O6 I/O5 VCCQ WE A12 A11 A10 A9 NC
Pin Description (1)
Symbol A0 to A17 I/O0 to l/O8 CLK CE WE OE VCCQ VCC VSS/VSSQ Description Address input Data input/output Clock Chip enable input Write enable input Output enable input Output power supply +5V power supply Ground
Block Diagram
CLK CE WE OE Register CLK A0 A17 Register CLK I/O8 Register Decoder Self-Timed Write Logic
256KX9 RAM
CLK Register CLK
Sense Amp Register
I/O0
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CXK77920TM/YM
Pin Description (2) CLK (Clock, positive edge triggered) All timing is controlled by the rising or positive edge of CLK. All synchronous input and output signals are registered on the positive edge of CLK with set-up and hold times referenced to that edge. Since only one edge of CLK is referenced, the duty cycle of CLK is not critical. A0 to A17 (Address) The Address inputs are decoded on-chip to select one of 262,144 words. The state of the Address inputs is registered into the Address register on the positive edge of CLK. The Address inputs must be valid during every positive edge with all set-up and hold times referenced to that edge. I/O0 to l/O8 (Data input/output) I/O terminals are three-state and data input/output common. The state is defined by the Control block (refer to the truth table on page 4). The data inputs for write operation must be valid during every positive edge of CLK with all set-up and hold times referenced to that edge. The data outputs are triggered by the positive edge of CLK and the contents of the Output-Registers are presented. WE (Synchronous Write Enable, active low) WE is used to indicate whether a read or write operation is to be performed. WE is "LOW" to perform a write operation. WE is registered on every positive edge of CLK with set-up and hold times referenced to that edge. The internal timing required to store data into the memory array is self-timed. CE (Synchronous Chip Enable, active low) CE is used to select the Synchronous SRAM when low (or deselect when high). When selected, the Synchronous SRAM will perform a read or write operation (refer to the truth table on page 4). The state of CE is registered on every positive edge of CLK with set-up and hold times referenced to that edge. OE (Synchronous Output Enable, active low) OE is used to indicate that a read operation is to be performed. If the Synchronous SRAM is selected, the OE is low to perform a read operation (refer to the truth table on page 4). The state of OE is registered on every positive edge of CLK with set-up and hold times referenced to that edge.
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CXK77920TM/YM
Absolute Maximum Ratings
Item Supply voltage Input voltage Output voltage Allowable power dissipaiton Operating temperature Storage temperature Soldering temperature * time Symbol VCC VIN VO PD Topr Tstg Tsolder Rating -0.5 to +7.0
(Ta = +25C, GND = 0V)
Unit V V V W C C C sec
-0.5 to VCC+0.5 -0.5 to VCC+0.5 1.0 0 to +70 -55 to +150 235 * 10
Truth Table
CLK CE (tn) WE (tn) OE (tn) H L L L X H H L X H L X Mode Deselect Read Read Write I/O0 to l/O8 Hi-Z Hi-Z Data out (1) Data in VCC Current ISB ICC ICC ICC
NOTES: 1. Data comes out on the next positive edge of CLK. X: "H" or "L"
DC Recommended Operating Conditions
Item Supply voltage Output supply voltage Input high voltage Input low voltage Symbol VCC VCCQ VIH VIL Min. 4.75 3.15 2.2 -0.3(1) Typ. 5.0 -- -- --
(Ta = +25C, GND = 0V)
Max. 5.25 5.25 VCC +0.3 0.8 Unit V V V V
NOTE: 1. VIL = -1.5V min. for pulse width less than 1ns.
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CXK77920TM/YM
Electrical Characteristics DC Characteristics
Item Input leakage current Output leakage current Average operating current Standby current Output high voltage Output low voltage ISB VOH VOL Symbol ILI ILO ICC VIN = GND to VCC VO = GND to VCC OE = VIH Duty = 100% IOUT = 0mA CE VIH Cycle Min, Duty = 100% IOH = -2.0mA IOL = 4.0mA Cycle = 90MHz Cycle = 80MHz Cycle = 66.7MHz
(VCC = 5V 5%, GND = 0V, Ta = 0 to = +70C)
Test Conditions Min. -1 -1 -- -- -- -- 2.4 -- Max. 1 1 180 170 160 130 -- 0.4 mA V V mA Unit A A
I/O Capacitance
Item Input capacitance I/O capacitance Symbol CIN CI/O Test Conditions VIN = 0V Vl/O = 0V Min. -- --
(Ta = +25C, f = 1MHz)
Max. 5 7 Unit pF pF
NOTE: This parameter is sampled and is not 100% tested.
AC Characteristics AC Test Conditions
Item Input pulse high level Input pulse low level Input rise time Input fall time Input reference level Output reference level Output load conditions
(VCC = 5V5%, Ta = 0 to +70C)
Conditions VIH = 3.0V VIL = 0V tr = 3ns tf = 3ns 1.5V 1.5V Figure 1
*1. Including scope and jig capacitance. *2. tCKHQZ, tCKHQX 50pF*1 5pF*1 255 I/O I/O Output load (1) Output load (2)*2 5V 480
Figure 1
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CXK77920TM/YM
Read Cycle
Item Read cycle time Clock high pulse width Clock low pulse width Clock to data valid Address setup to clock high Address hold from clock high Chip enable setup to clock high Chip enable hold from clock high Output enable setup to clock high Output enable hold from clock high Clock high to output low-Z Clock high to output high-Z Symbol tCKHCKH tCKHCKL tCKLCKH tCKHQV tAVCKH tCKHAX tCEVCKH tCKHCEX tOEVCKH tCKHOEX tCKHQX(1) tCKHQZ(1) -11 Min. Max. 11 3.5 3.5 -- 2.5 0.5 2.5 0.5 2.5 0.5 1.5 -- -- -- -- 6.0 -- -- -- -- -- -- -- 4.5 -12 Min. Max. 12.5 4.0 4.0 -- 2.5 0.5 2.5 0.5 2.5 0.5 1.5 -- -- -- -- 6.5 -- -- -- -- -- -- -- 5.0 -15 Min. Max. 15 5.0 5.0 -- 3.0 0.5 3.0 0.5 3.0 0.5 1.5 -- -- -- -- 7.0 -- -- -- -- -- -- -- 6.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns
NOTE: 1. Transition is measured +200mV from steady voltage with specified loading in Figure 1-(2). This parameter is sampled and is not 100% tested.
Write Cycle
Item Read cycle time Clock high pulse width Clock low pulse width Address setup to clock high Address hold from clock high Chip enable setup to clock high Chip enable hold from clock high Write enable setup to clock high Write enable hold from clock high Input data setup to clock high Input data hold from clock high Symbol tCKHCKH tCKHCKL tCKLCKH tAVCKH tCKHAX tCEVCKH tCKHCEX tWEVCKH tCKHWEX tDVCKH tCKHDX -11 Min. Max. 11 3.5 3.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -12 Min. Max. 12.5 4.0 4.0 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -15 Min. Max. 15 5.0 5.0 3.0 0.5 3.0 0.5 3.0 0.5 3.0 0.5 -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns
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CXK77920TM/YM
Timing Waveform Read Cycle
CLK tAVCKH tCKHAX n tCKHCKH tCKHCKL tCKLCKH
Address
n+1
n+2
WE
tWEVCKH CE tCEVCKH
tCKHWEX
tCKHCEX
OE tOEVCKH tCKHOEX Data out Qn-2
(1)
tCKHQV Qn-1
(1)
Qn
(1)
NOTE: 1. Valid data from CLK high is the data from the previous cycle.
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CXK77920TM/YM
Write Cycle: OE = VIH or VIL
CLK tAVCKH tCKHAX n tCKHCKH tCKHCKL tCKLCKH
Address
n+1
n+2
tCEVCKH tCKHCEX CE
tWEVCKH tCKHWEX WE tOECKH tCKHOEX
OE tDVCKH tCKHDX
Data in
Dn
Dn+1
Dn+2
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CXK77920TM/YM
Read/Write Cycle
CLK tAVCKH tCKHAX tCKHCKH tCKHCKL tCKLCKH
Address
n
n+1
n+2
tCECKH tCKHCEX CE tWEVCKH tCKHWEX WE tOEVCKH tCKHOEX
OE tDVCKH tCKHDX
tCKHQX Qn+1 tCKHQV
I/O
Qn-2 tCKHQZ
Dn
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CXK77920TM/YM
Example of Representative Characteristics
Supply Current vs. Supply Voltage
1.4 ICC--Supply Current (Normalized) ICC--Supply Current (Normalized) 1.4
Supply Current vs. Ambient Temperature
1.2
1.2
1.0
ICC
ICC 1.0
0.8 Ta = +25C
0.8 VCC = 5.0V
0.6 4.5
5.25 4.75 5.0 VCC--Supply Voltage (V)
5.5
0.6 0 20 40 60 80 Ta--Ambient Temperature (C)
Supply Current vs. Frequency
1.2 tCKHQV -- Access Time (Normalized) 1.4
Access Time vs. Load Capacitance
ICC--Supply Current (Normalized)
1.0 Read, Write
1.2
0.8
1.0
0.6
VCC = 5.0V Ta = +25C
0.8 VCC = 5.0V Ta = +25C 0.6
0.4 20 40 60 80 100 Frequency (1/tCKHCKH) (MHz)
0
75 25 50 CL--Load Capacitance (pF)
100
Cycle Time (minimum) / Access Time vs. Supply Voltage
1.4 tCKHCKH -- Cycle Time, tCKHQV -- Access Time (Normalized) tCKHCKH -- Cycle Time, tCKHQV -- Access Time (Normalized) 1.4
Cycle Time (minimum) / Access Time vs. Ambient Temperature
1.2
1.2
tCKHQV 1.0 tCKHCKH
tCKHQV tCKHCKH
tCKHCKH 1.0 tCKHQV 0.8 VCC = 5.0V
0.8 Ta = +25C
0.6 4.5
4.75
5.0
5.25
5.5
0.6
0
20
40
60
80
VCC--Supply Voltage (V)
Ta--Ambient Temperature (C)
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CXK77920TM/YM
Standby Current vs. Supply Voltage
1.4 ISB--Standby Current (Normalized) ISB--Standby Current (Normalized) 1.8
Standby Current vs. Ambient Temperature
1.2
1.4
ISB 1.0
1.0
0.8 Ta = +25C
0.6 VCC = 5.0V
0.6 4.5
0.2 4.75 5.0 5.25 5.5 0 20 40 60 80 VCC--Supply Voltage (V) Ta--Ambient Temperature (C)
Input Voltage Level vs. Supply Voltage
1.4 VIL, VIH--Input Voltage (Normalized) VIL, VIH--Input Voltage (Normalized)
Input Voltage Level vs. Ambient Temperature
1.4
1.2
1.2
VIH 1.0 VIL
1.0
VIH, VIL
0.8 Ta = +25C
0.8 VCC = 5.0V
0.6 4.5
0.6 4.75 5.0 5.25 5.5 0 20 40 60 80 VCC--Supply Voltage (V) Ta--Ambient Temperature (C)
Output Low Current vs. Output Low Voltage
1.8 IOL, Output Low Current (Normalized) IOH, Output High Current (Normalized)
Output High Current vs. Output High Voltage
4
1.4
3
VCC = 5.0V Ta = +25C
1.0
2
0.6 VCC = 5.0V Ta = +25C 0.2 0 0.2 0.4 0.6 0.8 VOL--Output Low Voltage (V)
1
0
0
1
2
3
4
VOH--Output High Voltage (V)
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CXK77920TM/YM
Package Dimensions Unit: mm CXK77920TM
44 PIN TSOP (II) (PLASTIC) 400MIL
1.2MAX *18.410.1 44 23 *10.160.1 11.760.2 0.1
A
1 0.8 B 0.30.1
22 0.13 M
+0.05 0.125-0.02
+0.1 0.1 -0.05
0.320.08 (0.3) (0.125)
0.1450.55
0-10
Detail A Detail B NOTE>Dimension "*" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSOP(II)-44P-L01 TSOP(II)044-P-0400-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 ALLOY 0.5g
CXK77920YM
44 PIN TSOP (II) (PLASTIC) 400MIL
1.2MAX *18.41 0.1 1 22 *10.160.1 11.760.2 0.1
A
44 0.8 B 0.30.1
23 0.13 M
+0.05 0.125-0.02
+0.1 0.1 -0.05
0.320.08 (0.3) (0.125)
0.1450.55
0-10
Detail A Detail B NOTE>Dimension "*" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSOP(II)-44P-L01R TSOP(II)044-P-0400-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 ALLOY 0.5g
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0.5 0.1
0.5 0.1

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